module AddrMUX(LessIn,ZeroIn,ResultIn,PCRelAddrIn,SeqAddrIn,SelectorIn,AddrOut);
  input LessIn;
  input ZeroIn;
  input [31:0]ResultIn;
  input [31:0]PCRelAddrIn;//PC+Offset
  input [31:0]SeqAddrIn;//PC+1
  input [2:0]SelectorIn;
  output reg[31:0]AddrOut;

  always@(*)begin
    case (SelectorIn)
      3'b000:AddrOut<=SeqAddrIn;
      3'b001:if(LessIn) AddrOut<=PCRelAddrIn;//blt
              else AddrOut<=SeqAddrIn;
      3'b010:if(ZeroIn) AddrOut<=PCRelAddrIn;//beq
              else AddrOut<=SeqAddrIn;
      3'b011:AddrOut<=PCRelAddrIn;//jal
      3'b100:AddrOut<=ResultIn;//jalr
    default:AddrOut<=SeqAddrIn;//其他情况按PC+1
    endcase
  end
endmodule
